Geek's Portal For Computers Graphics Operating Systems Multi-Media Networking Programming Data Format and  News
[ Start Page ] [ Contacting ] [ About ] [ Link To Us ] [ Geek Gear ] Thu, Nov 20 2008 
Free Internet Tools by web-geek.com Internet Tools
Administrator Tools
Name Server Look Up
Ping Test
Who Is
Trace Route

Web Developer Tools
Web Safe Colors
HTML Character Map
PopUp Generator
Body Color CSS v1.0
Browser Information
Meta Tag Generator
Keywords Generator
Link Popularity
JavaScript Escape / Unescape Converter
JavaScript Drop Down Menu Builder
Web / Virtual Hosting Directory

Reference Documention
HTML 4.0 Reference

Reference Tables
Character Conversion Table
Domain Name Suffixes

Cheat Sheets
Vi / Vim Basic Commands


WEB-GEEK.COM's Feature Sites Feature Sites
oGobogo Internet Search Directory
News.web-geek.com Internet News Directory
Pdawebgeek.com PDA Friendly Web Directory
Games.web-geek.com Free Online Games



folder Directories
Top > Computers > Hardware > Components > Processors > Minimal
MOVE Project Automatic Synthesis of Application Specific Processors. Goal: design, build high-performance processors via a new class of transport-triggered architectures, TTAs, programmed by specifying data-transports not operations; well suited for application specific uses.
Wikipedia: One Instruction Set Computer Online encyclopedia article about this single machine language opcode, with links to related articles.
Wikipedia: Transport Triggered Architectures Online encyclopedia article about this approach to computer architecture.
NASA: Space Related Applications of Forth Uses of Forth microprocessors and programming language: controllers for spacecraft flight systems, on-board payload experiments, ground support; hardware or software to build or test flight or ground systems.
SUBLEQ Simple one instruction language; type of OISC; specifications from Clive Gifford eigenratios self-interpreter page. Each subleq instruction has 3 operands which are memory addresses. Oleg Mazonka.
A No Instruction Set Processor Benefits: simple, easily pipelined, useful in self-clocked systems, very flexible and optimizable, good memory access, highly. Problems: awkward to program. [cowlark.com]
The Ultimate RISC Explains extreme, simple RISC, with only one instruction, move memory to memory; yet it is useful. Revision of paper first published in ACM Computer Architecture News.
MSL16 Processor Minimal instruction set, small, low power 16-bit CPU optimized to run Forth on a Xilinx FPGA. When system is stable, VHDL source code for CPU and all other code will be released to make a full open source public domain CPU.
Stack Computers & Forth Philip J. Koopman, Jr., CMU page. Reports, studies, and links. Compares: CISC, RISC, Stack systems; 2 and 3 stack systems.
Stack Computers: The New Wave By Philip J. Koopman, Jr; Ellis Horwood, 1989, ISBN 0470214678. Read on-line, or download in formats: HTML, PDF, zip file. First book to explore a new breed of stack computers led by introduction of Novix NC4016. [Free]
Enumera, Inc. Goal: dominate very low cost, low power, single core CPU market, and have the only ultra-high-end supercomputer on-a-chip system. Because the CPU core is so small, it is possible to put 1000s of cores and memory in one IC chip package.
Microprocessor Architectures from VLIW to TTA By Henk Corporaal; John Wiley, 1998, ISBN 047197157X. Introduces Transport Triggered Architectures, TTAs. In standard architectures, programmed operations trigger internal data transports. TTAs work by programming data transports themselves. This removes bottlenecks, allows for new code generation optimizations, uses hardware more efficiently.
Java Optimized Processor JOP is the implementation of a small java processor with the JVM fitting in a FPGA.
4stack Processor Research project for high performance, low cost computing. Uses stack-based instructions for a 4-way VLIW processor. Implemented in current technology, it would outrun high-end DSPs (TMS 320C6x, TigerSHARC), and let the full program run on one processor, with no further RISC core.
New Micros, Inc. Designs, builds: single board computers (SBC), peripherals, embedded systems, PCB design/layout, high level programming (industry leaders in Forth), custom design work; large line of stock products: from full handheld computers to development packages. Since 1980.
PTSC: Patriot Scientific Corp. Makes IGNITE I ROSC (Removed Operand Set Computer), PSC1000 32-bit embedded shBoom-based microprocessor line, many ISDN interface products, sophisticated antenna/radar technologies.
SandPiper Technology Course on minimal processors: Guided Exploration of two FPGA-based CPU Designs, led by John Rible.
E25 Computer Architecture: Lab 5: OISC: One Instruction Set Computer Class project to design and implement One Instruction Set Computer; using instruction: SUBLEQ A B C. Meaning: subtract value in M(A) from M(B) and store it in M(B), if result is not positive, go to instruction C. Descriptions, diagrams, code, tables.
Triangle Digital Services Ltd. Small, powerful Forth embedded computers: let you quickly design applications: controls, portable instruments, terminals, data loggers, GPS, CAN bus, multitasking, LCD and keyboard systems. High level language makes development simple and fast; needs no PROM programmer. Forth hardware and software.
Forth Chips References, links to Forth and stack machines in various technologies.
Minimal Instruction Set Computers Stack-based processors, 5-bit words, 25 instructions, 7000 transistors, 80 MIPS, 50 milliwatts, low cost; designed by Chuck Moore, creator of Forth programming language.
T-Recursive Technology Embedded systems consultant for small (8/16-bit) and distributed microprocessor systems. Contract hardware and software development for most microcontrollers. Specialist: Forth, Assembly, C. By Bradford J. Rodriguez, Ph.D.
Sponsor Sponsor


  © 1999-2006, web-geek.com a Geek Boy Enterprises, Inc. website terms and conditions of use [ Start Page ] [ Contacting ] [ About ] [ Link To US ]